Design Verification Engineer
Company: Apple Inc.
Location: Boston
Posted on: May 4, 2024
Job Description:
At Apple, we work every single day to craft products that enrich
people's lives. Do you love working on challenges that no one has
solved yet? Do you like changing the game? We have an opportunity
for a transformative and unusually talented design verification
engineer.As a member of our multifaceted group, you will have the
rare and exciting opportunity to craft upcoming products that will
delight and encourage millions of Apple's customers every single
day. Do your life's best work here at Apple! This role is for a DV
engineer who will enable bug-free first silicon for the IP designs.
The responsibilities include all phases of pre-silicon verification
including but not limited to: establishing DV methodology,
test-plan development, verification environment development
including stimulus and checkers, test-writing, debug, coverage,
sign-off for RTL freeze and tape-out. Key Qualifications
- Good proven understanding of System Verilog test-bench language
and UVM
- Validated experience developing scalable and portable
test-benches
- Shown experience with verification methodologies and tools such
as simulators, waveform viewers, build/run automation, coverage
collection, gate level simulations
- Experience with IP verification methodology
- In lieu of UVM knowledge, C/C++ knowledge
- Significant experience with DDR PHY/Controller and/or High
Speed SerDes
- Deep knowledge of one of the scripting languages: Python, Perl,
TCL
- Knowledge of formal verification methodology a plus
- Knowledge of UPF definitely a plus Description In this role,
you will be responsible for ensuring bug-free first silicon for
part of the SoC / IP and are encouraged to the following:Develop
detailed test and coverage plans based on the micro-architecture.
Develop verification methodology suitable for the IP, ensuring
scalable and portable environment.Develop verification environment,
including all the respective components such as stimulus, checkers,
assertions, trackers, coverage.Develop verification plans for all
features under your care.Implement verification plans, including
design bring-up, DV environment bring-up, regression enabling for
all features under your care, debug of the test failures.Develop
block, IP and SoC level test-benches.Track and report DV progress
using a variety of metrics, including bugs and coverage.Develop IP
simulation environment, and work closely with analog team to ensure
overall bug-free IP designs. Education & Experience BS degree in
technical subject area with minimum 10 years of proven
experience.Apple is an Equal Opportunity Employer that is committed
to inclusion and diversity. We also take affirmative action to
offer employment and advancement opportunities to all applicants,
including minorities, women, protected veterans, and individuals
with disabilities. Apple will not discriminate or retaliate against
applicants who inquire about, disclose, or discuss their
compensation or that of other applicants.
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Keywords: Apple Inc., Brookline , Design Verification Engineer, Engineering , Boston, Massachusetts
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